SystemVerilog Event Regions

Hi All,

In the last post, we had discussed the Verilog Event Regions. Today we'll discuss the event regions in SystemVerilog, which are somewhat similar to the Verilog Event regions only, plus there are some additional regions as well.

Similar to Verilog, in Systemverilog also the event queue is divided into 5 different regions. A SystemVerilog simulator, shall maintain some form of data structure that allows events to be dynamically scheduled, executed, and removed as the simulator advances through time. Simulation proceeds by executing and removing all events in the current simulation time slot before moving on to the next nonempty time slot, in time order. And in that given simulation timeslot, it is necessary to execute events of all of the above mentioned regions.

Most important thing is that these regions encompass the Verilog Event Regions and hence the legacy Verilog code should run correctly without any modification in SystemVerilog simulator.

Prepone Region - It is used t…

Verilog Event Regions

Hi All,

Today we'll see about something important about Verilog language. We'll see the event regions of the Verilog and how does it affect the simulation process.

Please note that this is a conceptual model as per IEEE standard and how each vendor implemets this model, is completely proprietary.

Verilog is divided in the 4 event regions. And for any given time stamp, it is necessary to execute events of all region, before moving to the next time stamp (So if timescale is 1ns/10ps, then at every 10ps, events in all of the regions are evaluated, before moving to next simulation time)
Active Region - The active event region is the event region, where most of the Verilog events are scheduled including Blocking Assignment, Evaluation of RHS side of Nonblocking Assignments, Continuous Assignments, $display command execution and evaluation of i/p & o/p of primitives. However all of the sub events of the active region, can be executed in any order and is strictly vendor specific o…

Debugging on Class Based Testbench

Hi All,

Sorry for late post, as I had been busy with some personal work. Today we'll discuss about an important article, which I came across while surfing on internet for RTL Verification. This post does not contain any technical information from my side, but this is just to share a really good stuff.

In RTL verification, debugging is very much important to find out the exact bug. And sophisticated tools are available for RTL debugging. But for class based testbench, many times we don't have that previledge to check the annotation, of check the instance hierarchy or check the current value or check the schematic.

More and more semiconductor firms are adopting System Verilog based verification and in special, UVM methodology. Things become more complicated, when we have a full chip verification with multiple environement/agents/drivers in the system, simultaneously communicating with the DUT and transmitting/receiving informations.

So here, I am providing a link of "Debug…

What is Formal Verification through Model Checking? [2/2]

Hi All,

This is the 2nd post on the Formal Verification. Here we will discuss about the remaining topics of the Formal Verification through Model Checking.

Results of the Model Checking Now that, you know, that Model Checking is all about Properties, Constraints & Tool, we shall examine how tool works.
Now the job of the Model Checking tool is to verify User Defined Properties exhaustively, by satisfying the User Defined Constraints.
There are basically 3 types of results for any Property, Model Checking tool can give. Conclusive, Proven - Property is exhaustively verified, and you can be assured, that there is no bugin that piece of RTL.Conclusive, Falsified - Property has been failed. In this case, tool will provide you the Falsification Trace (Set of input pattern, which can make the property to fail)Inconclusive (Bounded Proof) - Tool can not confirm the proof or falsification of the property. In this case, tool will provide you the "Bounded Proof Depth", number of the…

What is Formal Verification through Model Checking? [1/2]

Hi All,

Sorry for the delay in the post. But you know, good content takes it's own time ;)

Today we will discuss about a relative new technology for verification, Formal Verification through Model Checking. I hope, you guys will know the fundamentals or theory of the Model Checking, by reading this post.

What is Formal Verification? Before knowing about Model Checking, we must know about Formal Verification. Formal Verification is an algorithmic based approach, to logic verification, that exhaustively proves functional properties of a design.Focus is not on Stimulus, but rather correctness of the reference.Proves or disapproves, correctness of the design mathematically.Most commonly used algorithms : BDD/ROBDD, SAT Solvers (We may talk about this algorithms in subsequent blog posts)
There are 2 types of the Formal Verification :

Equivalance Checking  - Verifies Functional Equivalence of 2 designs, which are at smae or different abstraction level. Like RTL to RTL, RTL to Gate Level, …

Standard Cell Based ASIC Design Flow

Hi All, 
Today we will discuss about ASIC Design Flow, as it is one of the most important and crucial thing to understand.

Now, we will try to get brief idea about each steps in the above image.

Specification - Specification of the system, like what is the functionality of system, what is the desired speed of the system, area constraint of the system, whether it has any power constraint or not, tolerances of various constraints, operative conditions of the system.RTL Description - Generally after specification, the system is partitioned into various blocks and RTL description (HDL Code like Verilog or VHDL), mostly in behaviour form is written. Sometimes Higher Level Language Code like C/C++ is also written, and in that case, a High Level Synthesis Tool is used, which converts the Higher Language Code into RTL Level Code. After RTL Coding, Functional Verification is done to check the correctness of the functionality.Logic Synthesis - Now, when your RTL Description is ready with correc…

How to implement more than 1 Analysis Implementation Ports in a Class in UVM

Hi All,

In this post, we will discuss about how to include more than 1 Analysis Implementation Port in a Class in UVM.

Analysis Ports are used for many purposes like Coverage Collection, Received/Transmitted Packet Checking. And sometimes, you may need to take coverage on different packets (so you will require different analysis implementation ports) and you do not want to define 2 different class, just for coverage.

So if there are more than 1 (suppose 2) analysis implementation ports in a class, then obvious (and the first also !!!) question arises in the mind is that, how to implement 2 write methods in the same class.

Well, in UVM, we have 2 different methods to address the problem.

Method - 1 : Use "imp" Suffix defined via MacroDeclare Macro `uvm_analysis_imp_decl(<Postfix>) outside of the component. This macro adds post-fix to the analysis implementation port class name and associated write method.Instantiate Analysis Implementation Port with uvm_analysis_imp_<…