VLSI RANDOM

Hi All,  Today we will discuss about ASIC Design Flow, as it is one of the most important and crucial thing to understand. ASIC Design Flow Now, we will try to get brief idea about each steps in the above image. Specification  - Specification of the system, like what is the functionality of system, what is the desired speed of the system, area constraint of the system, whether it has any power constraint or not, tolerances of various constraints, operative conditions of the system. RTL Description  - Generally after specification, the system is partitioned into various blocks and RTL description (HDL Code like Verilog or VHDL), mostly in behaviour form is written. Sometimes Higher Level Language Code like C/C++ is also written, and in that case, a High Level Synthesis Tool is used, which converts the Higher Language Code into RTL Level Code. After RTL Coding, Functional Verification is done to check the correctness of the functionality. Logic Synthesis  - Now, wh

Hi All, In this post, we will discuss about how to include more than 1 Analysis Implementation Port in a Class in UVM. Analysis Ports are used for many purposes like Coverage Collection, Received/Transmitted Packet Checking. And sometimes, you may need to take coverage on different packets (so you will require different analysis implementation ports) and you do not want to define 2 different class, just for coverage. So if there are more than 1 (suppose 2) analysis implementation ports in a class, then obvious (and the first also !!!) question arises in the mind is that, how to implement 2 write methods in the same class. Well, in UVM, we have 2 different methods to address the problem. Method - 1 : Use "imp" Suffix defined via Macro Declare Macro `uvm_analysis_imp_decl(<Postfix>) outside of the component. This macro adds post-fix to the analysis implementation port class name and associated write method. Instantiate Analysis Implementation Port with u