VLSI RANDOM

Hi All, In the last post, we had discussed the Verilog Event Regions. Today we'll discuss the event regions in SystemVerilog, which are somewhat similar to the Verilog Event regions only, plus there are some additional regions as well. Similar to Verilog, in Systemverilog also the event queue is divided into 5 different regions. A SystemVerilog simulator, shall maintain some form of data structure that allows events to be dynamically scheduled, executed, and removed as the simulator advances through time. Simulation proceeds by executing and removing all events in the current simulation time slot before moving on to the next nonempty time slot, in time order. And in that given simulation timeslot, it is necessary to execute events of all of the above mentioned regions. Most important thing is that these regions encompass the Verilog Event Regions and hence the legacy Verilog code should run correctly without any modification in SystemVerilog simulator. Prepone Region...

Hi All, Today we'll see about something important about Verilog language. We'll see the event regions of the Verilog and how does it affect the simulation process. Verilog Event Regions Please note that this is a conceptual model as per IEEE standard and how each vendor implemets this model, is completely proprietary. Verilog is divided in the 4 event regions. And for any given time stamp, it is necessary to execute events of all region, before moving to the next time stamp (So if timescale is 1ns/10ps, then at every 10ps, events in all of the regions are evaluated, before moving to next simulation time) Active Region  -  The active event region is the event region, where most of the Verilog events are scheduled including Blocking Assignment, Evaluation of RHS side of Nonblocking Assignments, Continuous Assignments, $display command execution and evaluation of i/p & o/p of primitives.  However all of the sub events of the active region, can be execu...

Hi All, Sorry for late post, as I had been busy with some personal work. Today we'll discuss about an important article, which I came across while surfing on internet for RTL Verification. This post does not contain any technical information from my side, but this is just to share a really good stuff. In RTL verification, debugging is very much important to find out the exact bug. And sophisticated tools are available for RTL debugging. But for class based testbench, many times we don't have that previledge to check the annotation, of check the instance hierarchy or check the current value or check the schematic. More and more semiconductor firms are adopting System Verilog based verification and in special, UVM methodology. Things become more complicated, when we have a full chip verification with multiple environement/agents/drivers in the system, simultaneously communicating with the DUT and transmitting/receiving informations. So here, I am providing a link of ...

Hi All, In this post, we will discuss about how to include more than 1 Analysis Implementation Port in a Class in UVM. Analysis Ports are used for many purposes like Coverage Collection, Received/Transmitted Packet Checking. And sometimes, you may need to take coverage on different packets (so you will require different analysis implementation ports) and you do not want to define 2 different class, just for coverage. So if there are more than 1 (suppose 2) analysis implementation ports in a class, then obvious (and the first also !!!) question arises in the mind is that, how to implement 2 write methods in the same class. Well, in UVM, we have 2 different methods to address the problem. Method - 1 : Use "imp" Suffix defined via Macro Declare Macro `uvm_analysis_imp_decl(<Postfix>) outside of the component. This macro adds post-fix to the analysis implementation port class name and associated write method. Instantiate Analysis Implementation Port with u...

Hi All, This post is related to unexpected Simulation Behaviour with an Associative Array having 64 Bit Index in QuestaSIM. I had faced this problem and thought many others may have faced it also. So it is worth sharing the solution over here. NOTE :- This behaviour was observed in QuestaSIM 10.2. It may or may not be observed in the same or other versions of QuestaSIM. SAMPLE CODE :  Here is the sample code : typedef struct packed {   bit [7:0] data;   bit        valid; } dword_memory_st; ` define key 64 program p;   int loop_count;   int iteration; // Try with more than 8 to get the Errors ;)   dword_memory_st MEMORY[ bit [`key-1:0] ];   bit [`key-1:0] st = 'hffff_ffff_ffff_fffa;   bit [`key-1:0] ft = 'hffff_ffff_ffff_ffff;    bit [`key-1:0]  temp;    bit [`key:0]  max_memory_address = (1 << `key);    bit  bounded_address_used = 0; ...