Standard Cell Based ASIC Design Flow

Hi All, 

Today we will discuss about ASIC Design Flow, as it is one of the most important and crucial thing to understand.

ASIC Design Flow

Now, we will try to get brief idea about each steps in the above image.

• Specification - Specification of the system, like what is the functionality of system, what is the desired speed of the system, area constraint of the system, whether it has any power constraint or not, tolerances of various constraints, operative conditions of the system.
• RTL Description - Generally after specification, the system is partitioned into various blocks and RTL description (HDL Code like Verilog or VHDL), mostly in behaviour form is written. Sometimes Higher Level Language Code like C/C++ is also written, and in that case, a High Level Synthesis Tool is used, which converts the Higher Language Code into RTL Level Code. After RTL Coding, Functional Verification is done to check the correctness of the functionality.
• Logic Synthesis - Now, when your RTL Description is ready with correct functionality, you need to map that code into something, which can be fabricated on Silicon Wafer. Here it comes the part of Logic Synthesis. Logic Synthesis typically contains 2 process - Synthesis & Technology Mapping. Synthesis is the process, where logic will be optimized, to reduce the number of required gates. Technology Mapping is the process, where optimized logic will be mapped into actual standard cells available in the library. Logic Synthesis also adds Testability related hardware, which will be useful to find the Manufacturing Faults after Fabrication.
• Timing Analysis - After Logic Synthesis, what you get is the netlist (set of interconnected standard cells). Now in sequential circuits, timing is the most stringent criteria, that must be followed in order to have proper operation of the sequential element. In this timing analysis, combination cell delays, setup & hold timing violations are checked. This is a very important step, and often this is the sign-off criteria for front-end design. Note that, at this point of time, interconnection delays between different standard cells will not be known, but still this step is important in order to check, whether different combination portion of the chip behaves according to timing requirement or not. In practice, after logic synthesis or timing check, again verification of netlist is done, which is called Gate Level Simulation, in order to check, whether synthesis process has altered any functionality or not.
• Floorplanning - It is same as the floorplanning of a house, in which  you identify where to put kitchen, bedrooms, balcony, living room. Most of the time in the industry, a chip is not made from scratch, but it contains several predefined modules or IPs. So in floorplanning, location of the IPs, location of the netlist, location of routing regions are finalized in terms of rectangular regions.
• Power Planning - This process contains Vdd & Ground routing, in order to satisfy the power requirements of different blocks. Generally in this routing, current carrying capacity is the main important concern, as each net must feed sufficient amount of current to the lower nets. For this metal wires or nets with different widths are typically used, where top most metal layer will have widest power nets (because it has to supply sufficient current to all lower layers).
• Placement- Different Standard Cells are placed in the predefined regions of the chip. Here the most important consideration is to minimize the amount of net required to connect different cells. So while placing the cell, estimation of the net length is important, otherwise router may be unable to route all the nets or it may route the nets, but unable to meet the timing requirements.
• Clock Tree Synthesis - Clock is the most important signal in the sequential circuits. In the real chips, there will be only a single clock source, which shall be routed throughout the chip to connect various clock pins. In this process, clock shall be arrived at all location on same time for proper operation. So typically buffers are used, and clock tree synthesis essentially becomes a problem of putting buffer at appropriate places and route the clock nets such that all functional units get clock edge at the same time. And because of the complexity of the problem, clock tree synthesis is done differently than routing other nets. 
• Routing - Here nets between standard cells are routed, considering timing requirements, DRC errors, crosstalks between adjacent nets, parasitic capacitance, noise introduction. Routing is done in 2 process - Global Routing & Detailed Routing. Global Routing gives tentative route for each net, but does not give exact route. Whereas Detailed Routing provides exact routes for each net. Routing is a very complex problem & sometimes it takes almost as high as 30% of the design time. After routing, post layout timing analysis is done, with consideration of all standard cell delays and interconnect delays both. Often, after layout Circuit Extractor is used to extract the circuit and perform post layout simulation.
• Fabrication - After Routing, the GDS file is submitted to the foundary to fabricate the chip. After Fabrication also, Post Silicon Validation is performed, which checks whether functional blocks (digital and analog both) performs as per specification or not.

In reality, ASIC design flow is one of the most complex processes, and each steps above mentioned, contains long series of steps, in itself. More importantly, Fabrication of a chip is a very costly process and failure after manufacturing may lead to the huge amount of loss, so at each and every step in the above process, some kind of verification is performed.

Please feel free to ask or suggest any question or changes for the content.