VLSI RANDOM

Hi All, Sorry for late post, as I had been busy with some personal work. Today we'll discuss about an important article, which I came across while surfing on internet for RTL Verification. This post does not contain any technical information from my side, but this is just to share a really good stuff. In RTL verification, debugging is very much important to find out the exact bug. And sophisticated tools are available for RTL debugging. But for class based testbench, many times we don't have that previledge to check the annotation, of check the instance hierarchy or check the current value or check the schematic. More and more semiconductor firms are adopting System Verilog based verification and in special, UVM methodology. Things become more complicated, when we have a full chip verification with multiple environement/agents/drivers in the system, simultaneously communicating with the DUT and transmitting/receiving informations. So here, I am providing a link of ...

Hi All, In this post, we will discuss about how to include more than 1 Analysis Implementation Port in a Class in UVM. Analysis Ports are used for many purposes like Coverage Collection, Received/Transmitted Packet Checking. And sometimes, you may need to take coverage on different packets (so you will require different analysis implementation ports) and you do not want to define 2 different class, just for coverage. So if there are more than 1 (suppose 2) analysis implementation ports in a class, then obvious (and the first also !!!) question arises in the mind is that, how to implement 2 write methods in the same class. Well, in UVM, we have 2 different methods to address the problem. Method - 1 : Use "imp" Suffix defined via Macro Declare Macro `uvm_analysis_imp_decl(<Postfix>) outside of the component. This macro adds post-fix to the analysis implementation port class name and associated write method. Instantiate Analysis Implementation Port with u...