VLSI RANDOM

Hi All, Today we'll see about something important about Verilog language. We'll see the event regions of the Verilog and how does it affect the simulation process. Verilog Event Regions Please note that this is a conceptual model as per IEEE standard and how each vendor implemets this model, is completely proprietary. Verilog is divided in the 4 event regions. And for any given time stamp, it is necessary to execute events of all region, before moving to the next time stamp (So if timescale is 1ns/10ps, then at every 10ps, events in all of the regions are evaluated, before moving to next simulation time) Active Region  -  The active event region is the event region, where most of the Verilog events are scheduled including Blocking Assignment, Evaluation of RHS side of Nonblocking Assignments, Continuous Assignments, $display command execution and evaluation of i/p & o/p of primitives.  However all of the sub events of the active region, can be executed in

Hi All, Sorry for late post, as I had been busy with some personal work. Today we'll discuss about an important article, which I came across while surfing on internet for RTL Verification. This post does not contain any technical information from my side, but this is just to share a really good stuff. In RTL verification, debugging is very much important to find out the exact bug. And sophisticated tools are available for RTL debugging. But for class based testbench, many times we don't have that previledge to check the annotation, of check the instance hierarchy or check the current value or check the schematic. More and more semiconductor firms are adopting System Verilog based verification and in special, UVM methodology. Things become more complicated, when we have a full chip verification with multiple environement/agents/drivers in the system, simultaneously communicating with the DUT and transmitting/receiving informations. So here, I am providing a link of &quo

Hi All, This is the 2nd post on the Formal Verification. Here we will discuss about the remaining topics of the Formal Verification through Model Checking. Results of the Model Checking Now that, you know, that Model Checking is all about Properties, Constraints & Tool, we shall examine how tool works. Now the job of the Model Checking tool is to verify User Defined Properties exhaustively, by satisfying the User Defined Constraints. There are basically 3 types of results for any Property, Model Checking tool can give. Conclusive, Proven - Property is exhaustively verified, and you can be assured, that there is no bug in that piece of RTL. Conclusive, Falsified - Property has been failed. In this case, tool will provide you the Falsification Trace (Set of input pattern, which can make the property to fail) Inconclusive (Bounded Proof) - Tool can not confirm the proof or falsification of the property. In this case, tool will provide you the "Bounded Proof

Hi All, Sorry for the delay in the post. But you know, good content takes it's own time ;) Today we will discuss about a relative new technology for verification, Formal Verification through Model Checking. I hope, you guys will know the fundamentals or theory of the Model Checking, by reading this post. What is Formal Verification? Before knowing about Model Checking, we must know about Formal Verification. Formal Verification is an algorithmic based approach, to logic verification, that exhaustively proves functional properties of a design. Focus is not on Stimulus, but rather correctness of the reference. Proves or disapproves, correctness of the design mathematically. Most commonly used algorithms : BDD/ROBDD, SAT Solvers (We may talk about this algorithms in subsequent blog posts) There are 2 types of the Formal Verification : Equivalance Checking  - Verifies Functional Equivalence of 2 designs, which are at smae or different abstraction level. Like R