Debugging on Class Based Testbench

Hi All,

Sorry for late post, as I had been busy with some personal work. Today we'll discuss about an important article, which I came across while surfing on internet for RTL Verification. This post does not contain any technical information from my side, but this is just to share a really good stuff.

In RTL verification, debugging is very much important to find out the exact bug. And sophisticated tools are available for RTL debugging. But for class based testbench, many times we don't have that previledge to check the annotation, of check the instance hierarchy or check the current value or check the schematic.

More and more semiconductor firms are adopting System Verilog based verification and in special, UVM methodology. Things become more complicated, when we have a full chip verification with multiple environement/agents/drivers in the system, simultaneously communicating with the DUT and transmitting/receiving informations.

So here, I am providing a link of "Debugging of Class Based Testbench", with Mentor Graphics tool.

https://verificationacademy.com/verification-horizons/june-2014-volume-10-issue-2/Visualizer-Debug-Environment-Class-based-Testbench-Debugging-using-a-New-School-Debugger-Debug-This

Hope, if you are using Mentor Graphics Tools for simulation & verification, then the information in the above article will help you.

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