SystemVerilog Event Regions

Hi All,

In the last post, we had discussed the Verilog Event Regions. Today we'll discuss the event regions in SystemVerilog, which are somewhat similar to the Verilog Event regions only, plus there are some additional regions as well.




Similar to Verilog, in Systemverilog also the event queue is divided into 5 different regions. A SystemVerilog simulator, shall maintain some form of data structure that allows events to be dynamically scheduled, executed, and removed as the simulator advances through time. Simulation proceeds by executing and removing all events in the current simulation time slot before moving on to the next nonempty time slot, in time order. And in that given simulation timeslot, it is necessary to execute events of all of the above mentioned regions.

Most important thing is that these regions encompass the Verilog Event Regions and hence the legacy Verilog code should run correctly without any modification in SystemVerilog simulator.

  • Prepone Region - 
    • It is used to sample data immediately before entering into current timeslot. Sampling in current timeslot preponed region is equal to sampling data in previous timeslot postponed region.
    • Concurrent assertion data sampling is done in this region.
  • Active Event Queues - 
    • It is set of 3 Verilog event queues - Active Region, Inactive Region & NBA Region. The execution and meaning of these 3 regions are exactly same as that in Verilog.
  • Observed Region - 
    • It is to evaluate the property expressions, if they are triggered in the current timeslot.
  • Reactive Event Queues -
    • It is dual of the Active region set.
    • It is also set of 3 event queues - Active Region, Inactive Region & NBA Region, which behaves same as that in Verilog.
    • Code specified in the `program ..... endprogram` block & action blocks of the concurrent assertions are scheduled in this region. 
    • Main reason for this region is to differentiate the execution of RTL Code & Testbench Code and hence to eliminate the race condition between them.
  • Postpone Region - 
    • $monitor, $strobe events are scheduled in this event region.
    • No new changes in the value of any net/register is allowed in this event region. It is illegal to change any net value here.
I know it might be a bit difficult to grasp these concepts, if you haven't ever worked on SystemVerilog language. I shall try to more clarify it in the further posts with relevant examples (hopefully).

Feel free to ask questions, if any.


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